Recently, electrically erasable and programmable nonvolatile semiconductor memory devices (hereinafter referred to as EEPROMs) have become more and more highly integrated, considerably complicating various circuits within the memory devices. Accordingly, a memory device with NAND structure cells which are suitable for high integration has been widely used. The memory device with NAND structure cells is typically constructed to comprise a memory cell array divided into a plurality of memory blocks each sharing one word line row decoder, which can select any one of the memory blocks in response to a block selection signal, thereby performing a predetermined operation. This EEPROM with NAND structure cells is disclosed in the Apr. 1991 IEEE JOURNAL OF SOLID STATE CIRCUITS, Vol. 26, No. 4, pp. 492-495.
Conventional EEPROMs include a redundancy cell array for repairing the defects produced during the manufacturing process. If a memory block cannot operate normally due to defects therein, it is replaced by a defect repairing memory block within the redundancy cell array. It is customary to test the operation of EEPROMs while still in a wafer state (i.e. at the completion of the manufacturing process before separating the individual EEPROMs) to detect and replace the defective memory block by a repairing memory block within the redundancy cell array. This defect repairing method becomes useful as the memory device becomes highly integrated. Particularly, it becomes more useful with the gradual decrease of a minimum feature size to submicron range, which increases the likelihood of defects being attributable to short-circuits between the signal lines--e.g., a short-circuit between adjacent word lines, or a short-circuit between a word line and a string selection line, or a short-circuit between a string selection line and a bit line. Short-circuits between signal lines can also occur where one signal line crosses over or under another.
In order to detect short-circuited signal lines of the types described in the previous paragraph, conventional EEPROMs program the corresponding memory block with common data and then read the data, comparing the read-out data to the corresponding initially programmed data to determine whether the memory block is defective. This procedure tends to take too long a test time. This is particularly so as the memory device becomes highly integrated., since defects caused by short-circuits between adjacent signal lines (e.g., adjacent word lines) tend to be more numerous. The test time can be reduced if it can be determined whether or not the memory block is defective without the procedure of erasing-programming-reading etc., but conventional EEPROMs are not constructed so as to make such a determination and accordingly need a long test time. Another problem arises in conventional EEPROMs in that, since these EEPROMs program the memory cell prior to reading and checking the programmed memory cell, if there is a problem in the programming process, the memory cell is repaired by the redundancy cell even when the memory cell is normal.
Accordingly, a method for more rapidly sensing a short-circuit between adjacent signal lines in an electrically erasable and programmable nonvolatile semiconductor memory device and circuitry for implementing the method were sought.